Scan diagnosis system and method

ABSTRACT

A scan diagnosis system for testing and diagnosing a device-under-test is disclosed. The system includes a semiconductor tester adapted for coupling to the device-under-test and operative to generate pattern signals in the ATE domain to test the device-under-test and produce test output data in the ATE domain. An ATPG diagnosis tool is operative to generate ATPG pattern data and ATPG results data in the ATPG domain. A translator serves to effect automatic correlation of data between the ATPG domain and the ATE domain to allow data communication between the tester and the tool.

FIELD OF THE INVENTION

[0001] The invention relates generally to automatic test equipment andmore particularly a scan diagnosis system and method for designing,testing and diagnosing semiconductor devices.

BACKGROUND OF THE INVENTION

[0002] Conventional automatic test equipment (ATE) tests semiconductordevices using the functional test approach. The goal of the functionaltest approach is to verify that the device performs its intendedfunction under a variety of realistic operating conditions. Use of thefunctional test approach typically requires the generation of functionaltest patterns which exercise the device through its external interface.

[0003] However, as device complexities and densities increase, the costof the conventional functional test approach can increase dramatically.In particular, the volume of functional test pattern data required toachieve acceptable fault coverage may increase exponentially with thesize of the device. To offset these costs, many semiconductormanufacturers have looked towards structured design-for-testability(DFT) methods. With structured DFT methods the goal changes fromverification of functionality to finding manufacturing defects. Thesemethods generally rely on additional circuitry provided on the device toenhance the controllability and observability of the internal state ofthe device.

[0004] “Scan testing” is one common DFT method which has been used totest semiconductor devices and printed circuit boards for many years.With scan testing, “scan chains” (serially connected chains of storagecells) are inserted into the design. To test such a device, signals arefirst shifted serially into the device through the primary input pins toinitialize the cells in the scan chain. Then the device is clocked forsome number of cycles to propagate each scan cell's value into theadjacent combinational logic, after which the output of that logic isrecaptured into the scan chain. Finally, the scan chain contents areserially shifted out of the device through its primary output pins andcompared to expected values. From a test generation perspective, theeffect of this approach is to make a sequential design appear like acombinational design with a larger number of pins, as scan cells behaveeffectively as pseudo inputs and outputs.

[0005] Nowadays, the generation of scan test patterns is performed byautomatic test pattern generation (ATPG) tools. ATPG tools use knowledgeof the device design and available scan chains to generate patternswhich target specific faults. This is in contrast with the functionaltest pattern generation approach, which generally produces test patternsto exercise device behaviors and later performs a fault coverage toolcheck to see which faults the patterns detect.

[0006] Some ATPG tools are also capable of performing diagnosis, whichis essentially the reverse of the pattern generation process. To performdiagnosis, the ATPG tool reads a list of observed scan cell failures fora given pattern and determines a gate or set of gates which wouldexplain the failures if those gates had certain manufacturing defects.

[0007] However, to make use of these tools, the device must generally betested using the ATPG patterns, and the failures captured on the testermust somehow be routed back to the diagnosis tool. At a minimum, thisoften requires pattern conversion (converting the ATPG pattern into amanufacturing tester pattern) and result conversion (converting theoutput of the manufacturing tester into a format readable by thediagnosis tool). Pattern conversion involves translation from the ATPGpattern format (usually STIL or WGL for scan patterns) into theproprietary test pattern format of the manufacturing tester. Resultconversion involves translation from the domain of failing ATE patternnames and addresses to the domain of failing scan cells relative to ATPGpattern names. Therefore, result translation generally requires someknowledge of how the ATPG patterns were translated into manufacturingtest patterns, thus complicating the process.

[0008] Once results are converted into the appropriate form for thediagnosis tool, the diagnosis tool can be invoked to perform diagnosison the scan failures, producing logical defect data. From this point on,other available tools may be used to translate the logical defect datainto the physical locations of the defects, and then to analyze thephysical failures at these locations to determine the underlying causesand possible remedies.

[0009] For example, Maier and Smith describe an improved diagnosticprocess in their article entitled “A New Diagnostic Methodology.” Theirprocess first involves translation of logical diagnosis results such asproduced by the process described here into physical locations which canthen be combined with in-line electrical test data such as that producedby optical inspection equipment. By correlating test failures tophysical defects, they allegedly reduce the number of hardware samplessubmitted to failure analysis technicians. This allegedly reduces thenormally long turnaround time it takes to get feedback from diagnosticdata. The specific mapping tools described include a wafermap tool whichoverlays electrical test data with optical inspection data.Additionally, a per-die layout-oriented mapping tool is provided tosupport the accumulation of multiple data sets to identify “hot spots”in the device design.

[0010] While the conventional techniques described above are beneficialfor their intended purposes, the lack of automation between the ATE andthe diagnosis tool is problematic. Existing pattern conversion tools arenot integrated with the result translation process, so existing resulttranslation solutions generally embed knowledge about the particularATPG/diagnosis tool, pattern conversion tool, ATE, test program, and/ordevice and must therefore be modified when any of these changes.Moreover, the failure data identified and processed is typically notreadily user-comprehensible. The scan diagnosis system and method of thepresent invention addresses these problems.

SUMMARY OF THE INVENTION

[0011] The scan diagnosis system and method of the present inventionprovides a unique automated and visual approach to testing semiconductordevices with ATE and DFT tools. This minimizes diagnosis time fordevices-under-test, thereby optimizing the design-to-productiontimetable for semiconductor devices.

[0012] To realize the foregoing advantages, the invention in one formcomprises a scan diagnosis system for testing and diagnosing adevice-under-test. The system includes a semiconductor tester adaptedfor coupling to the device-under-test and operative to generate patternsignals in the ATE domain to test the device-under-test and produce testoutput data in the ATE domain. An ATPG diagnosis tool is operative togenerate ATPG pattern data and ATPG results data in the ATPG domain. Atranslator serves to effect automatic correlation of data between theATPG domain and the ATE domain to allow data communication between thetester and the tool.

[0013] In another form, the invention comprises a scan diagnosis systemincluding a test and diagnosis engine and a graphical-user-interface.The test and diagnosis engine includes a semiconductor tester and a scandiagnosis tool. The graphical-user-interface includes a generator forreceiving failure scan chain data identifying failed scan chains fromthe test and diagnosis engine and generating graphical representationsof the failed scan chains. The GUI further includes a display devicecoupled to receive the graphical representations from the graphical userinterface. The display device is operative to display the graphicalrepresentations of the failed scan chains.

[0014] In a further form, the invention comprises a method including thesteps of testing a device-under-test with test pattern data in a scanformat; capturing scan failure data associated with failed scan chainsfrom the device-under-test; displaying a portion of the scan chainsincluding the captured failure data; and diagnosing the scan failuredata with a diagnosis tool to produce diagnosis results data.

[0015] Other features and advantages of the present invention will beapparent from the following detailed description when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The invention will be better understood by reference to thefollowing more detailed description and accompanying drawings in which

[0017]FIG. 1 is a simplified block diagram of a scan diagnosis systemaccording to one form of the present invention;

[0018]FIG. 2 is a block diagram illustrating the test result translatorshown in FIG. 1;

[0019]FIG. 3 is a block diagram similar to FIG. 2, illustrating thediagnosis result translator of FIG. 1;

[0020]FIG. 4 is a partial flowchart illustrating the scan method of thepresent invention carried out by the scan system shown in FIG. 1;

[0021]FIG. 5 is a partial flowchart of the method of FIG. 4; and

[0022] FIGS. 6-8 are screens illustrating various options and resultsprovided by the GUI of FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

[0023] Electronic design automation (EDA) software gives semiconductordevice manufacturers a tool for troubleshooting and refining theircircuit designs before entering mass production. Employing EDA toolswith production-oriented ATE provides real-world test solutions not onlyfor the pre-production stage, but also in post-production where newfailures may materialize that might be indetectable through simulationalone. The present invention seamlessly integrates EDA software with theATE software to create a scan diagnosis system, generally designated 20(FIG. 1), to fully automate the process.

[0024] Referring to FIG. 1, the scan diagnosis system 20 employs a testand diagnosis engine 30 that couples to a device-under-test (DUT) 22. Agraphical-user-interface (GUI) 60 ties-in to the test and diagnosisengine to provide real-time visual monitoring of the various functionsprovided by the present invention, more fully described below.

[0025] Further referring to FIG. 1, the test and diagnosis engine 30includes automatic test equipment (ATE) in the form of a semiconductortester 32. The tester includes ATE-specific software for generating testvectors or patterns necessary to test the DUT 22. To take advantage ofthe DFT gates, or scan chains, provided on the DUT to enable scantesting, the ATE-specific software is supplemented by an EDA tool 34.

[0026] The EDA tool 34 includes a diagnosis engine 38 for evaluatingconverted output data from the ATE 32 for scan diagnosis. One of thebenefits of the EDA tool 34, besides diagnosing scan failure data, isthe ability to generate ATPG patterns that access specified scan chainsdisposed in the DUT 22. An ATPG generator 36 within the diagnosis toolprovides this capability.

[0027] Further referring to FIG. 1, respective pattern, test anddiagnosis results translators 40, 50 and 70 convert data used by the ATE32 and the EDA tool 34 to provide an automatic and seamless integrationbetween the software packages. The pattern translator 40 performs ATPGto ATE vector conversion, and generates test patterns which may becompiled and loaded onto the ATE. The pattern translator also includes amap generation component 42 which generates a pattern map (shown asdirect data at 43) between ATE and ATPG pattern domains and alsocaptures information describing the locations of scan load/unloadsequences within the ATE/ATPG patterns.

[0028] Referring now to FIG. 2, the test result translator 50, infurther detail, includes a first converter T1, which takes theATE-specific ASCII output data from the tester 32, referred to asdatalog data, (essentially a list of failing vectors in the ATE domainindicating the failing ATE patterns, addresses, cycles, and devicepins), and converts it into a general datalog format in the ATPG domain(referencing ATPG pattern names). The general datalog format combineselements of both the ATE and ATPG data formats. Additionally,correlation data from the mapping generator also feeds into theconverter T1 to associate scan chain location data with the vectorpattern data.

[0029] A series of functions are operable on the general datalog throughthe functional block A1, such as filtering, sorting, accumulating andquerying of data. The results of these functions are viewable by a userthrough optional selection menus in the GUI 60.

[0030] The general datalog is then converted by a second converter T2,into a general datalog domain that includes ATPG information. This datais is optionally processed through block A2, and subject to filtering,accumulating, etc. A third conversion is performed by converter T3,where the general datalog ATPG data is transformed into scan-cellfailure domain data, indicating ATPG pattern names, scan chain names,and scan cell numbers. Like the general datalog data, the general scancell failure data is subject to processing through block A3 (filtering,sorting, accumulating, querying) as desired. A fourth converter T4, thentakes the general scan cell failure data and transforms it into a formatsuitable for the specific diagnosis tool employed.

[0031] The diagnosis result translator 70, shown in FIG. 3, feeds ATPGspecific data from the diagnosis engine 38, through converter T5 toproduce general diagnosis results. Functional block A5 provides optionaldata processing functions, as desired, such as filtering, accumulating,and the like.

[0032] As noted above, processing through the test and diagnosis engine30 is conveniently monitored by a user through menu selections on theGUI 60. The GUI includes several interactive screens (FIGS. 6 through 8)that present a user with an array of options to visualize data in anynumber of formats. This provides a user with maximum flexibility indetermining and diagnosing problem areas in a DUT design, and can beused to reduce the volume of data which must be processed by the nextstep, thus reducing turnaround time. Of particular significance is theability of the GUI to actually show sequences of scan chains for rapidevaluation by the user. This is more fully described below.

[0033] In operation, the test and diagnosis engine 30 cooperates withthe GUI 50 to effect automatic and seamless integration between the ATE32 and the diagnosis tool 34. The general steps of operation are shownin the flowchart of FIGS. 4 and 5, and briefly described below.

[0034] Initially, at step 100, the diagnosis tool 34 generates ATPG testpatterns designed to serially shift along the scan chains (flip-flopsdisposed within the DUT 22) to determine failures in areas of the devicenot normally accessible by conventional ATE patterns. In order to getthe patterns into the device, however, they must first be translatedinto the appropriate ATE vector format. As noted above, this isautomatically carried out by the pattern translator 40, at step 102. TheATE 32 then processes the vector data to test the DUT, at step 104,resulting in the capture of scan failure data, at step 106. The captureddata is then converted and processed by converter T1 and block A1 (FIG.2), at step 108, to produce general ATE datalog data.

[0035] With the scan failures detected and converted into general ATEdatalog, the user may view the failure data in tabular or graphicalformat, at step 110, with the GUI 60. FIG. 6 illustrates an example ofthe GUI screen with a variety of options available to the user. Bothgraphical and tabular formats may be selected, with the resulting screenshowing the current and/or cumulative sequence of scan chains with thefailures highlighted. If multiple tests are performed on one or moredevices, the user can access accumulated data to view compiled resultsin a variety of ways.

[0036] From this point, the user then directs the translation of the ATEdatalog output data into the general ATPG datalog format with converterT2 and block A2, at step 112. The general ATPG datalog data may then bedisplayed, at step 114.

[0037] The translation process continues, as shown in FIG. 5, with thefurther conversion of the data from the general ATPG datalog intogeneral scan-cell failure data with converter T3, at step 116. This datamay be viewed, at step 118, by the GUI 60. To ready the data fordiagnosis, a fourth conversion is performed by converter T4, at step120, thereby translating the data from general scan-cell failures to thespecific EDA tool input data necessary for diagnosis.

[0038] With the fully data converted, the diagnosis tool may then bedirected, at step 122, to diagnose the scan failures. Following a fifthdata conversion by the diagnosis results translator 70, with T5, at step124, the results of the diagnosis may then be viewed by a user aslogical defect data, at step 126. FIGS. 5 and 6 illustrate screensshowing available options and results associated with these steps asreflected in the GUI 60.

[0039] After diagnosis processing, the data may be further processed, asdesired by the user. In some instances, the user may want to view aphysical design map for the device to further understand the defectsdiagnosed. This may be accomplished through the use of additionalsoftware, such as that available from Knights Technologies, and knownunder the trademark “LogicMap” TM.

[0040] Once the diagnosis is complete, the device manufacturer may usethe data to determine those steps in the manufacturing process or thedevice design that appear to be problematic. By correcting anydeficiencies in a timely manner, the delay between device design andhigh-volume production may be reduced.

[0041] Those skilled in the art will appreciate the many benefits andadvantages afforded by the present invention. Of significant importanceis the automation capability provided by the translators, which serve toseamlessly convert data between the respective ATE and EDA tool domains.This eliminates the need for costly and untimely batch processing toprocess data from one format to another. Further, by providing aflexible GUI that monitors all phases of the test and diagnosis,including visually illustrating failing scan chain sequences, anunderstanding of the failures involved may be more easily comprehendedand addressed by the semiconductor device manufacturer.

[0042] While the invention has been particularly shown and describedwith reference to the preferred embodiments thereof, it will beunderstood by those skilled in the art that various changes in form anddetail may be made therein without departing from the spirit and scopeof the invention.

What is claimed is:
 1. A scan diagnosis system for testing anddiagnosing a device-under-test including: a semiconductor tester adaptedfor coupling to the device-under-test and operative to generate patternsignals in the ATE domain to test the device-under-test and produce testoutput data in the ATE domain; an ATPG diagnosis tool operative togenerate ATPG pattern data and ATPG results data in the ATPG domain; anda translator to effect automatic correlation of data between the ATPGdomain and the ATE domain to allow data communication between the testerand the tool.
 2. A scan diagnosis system according to claim 1 whereinthe translator includes: a pattern translator to convert ATPG patterndata into ATE pattern data; a result translator to convert ATE outputdata into ATPG tool input data; and a mapping generator for correlatingthe pattern data and the results data between the ATPG and the ATEdomains.
 3. A scan diagnosis system according to claim 1 and furtherincluding: a graphical user interface generator for receiving failurescan chain data identifying failed scan chains from the test anddiagnosis engine and generating graphical representations of the failedscan chains; and a display device coupled to receive the graphicalrepresentations from the graphical user interface, the display deviceoperative to display the graphical representations of the failed scanchains.
 4. A scan diagnosis system including: a test and diagnosisengine including a semiconductor tester and a scan diagnosis tool; agraphical user interface generator for receiving failure scan chain dataidentifying failed scan chains from the test and diagnosis engine andgenerating graphical representations of the failed scan chains; and adisplay device coupled to receive the graphical representations from thegraphical user interface, the display device operative to display thegraphical representations of the failed scan chains.
 5. A scan diagnosissystem according to claim 4 wherein the semiconductor tester isoperative to generate pattern signals in the ATE domain to test adevice-under-test and produce test output data in the ATE domain, andthe diagnosis tool is operative to generate ATPG pattern data and ATPGresults data in the ATPG domain, the scan diagnosis system furtherincluding: a translator to effect automatic correlation of data betweenthe ATPG domain and the ATE domain to allow data communication betweenthe tester and the tool.
 6. A scan diagnosis system according to claim 5wherein the translator includes: a pattern translator to convert ATPGpattern data into ATE pattern data; a result translator to convert ATEoutput data into ATPG tool input data; and a mapping generator forcorrelating the pattern data and the results data between the ATPG andthe ATE domains.
 7. A scan diagnosis system including: semiconductortester means for generating pattern signals in an ATE domain to test adevice-under-test and producing test output data in the ATE domain;diagnosis tool means for generating ATPG pattern data and ATPG resultsdata in an ATPG domain; and means for automatically correlating databetween the ATPG domain and the ATE domain to allow data communicationbetween the tester means and the tool means.
 8. A scan diagnosis systemaccording to claim 7 wherein the test output data includes failed scanchain data, the scan diagnosis system further including: means forgraphically displaying the failed scan chain data.
 9. Acomputer-readable medium having stored thereon sequences of instructionswhich, when executed, cause one or more electronic systems to: test adevice-under-test with test pattern data in a scan format; capture scanfailure data associated with failed scan chains from thedevice-under-test; display a portion of the scan chains including thecaptured failure data; and diagnose the scan failure data with adiagnosis tool.
 10. A method comprising: testing a device-under-testwith test pattern data in a scan format; capturing scan failure dataassociated with failed scan chains from the device-under-test;displaying a portion of the scan chains including the captured failuredata; and diagnosing the scan failure data with a diagnosis tool toproduce diagnosis results data.
 11. A method according to claim 10wherein the step of testing includes the step: directly communicatingwith the diagnosis tool.
 12. A method according to claim 10 wherein thestep of testing includes the step: generating ATPG pattern data in theATPG domain with the diagnosis tool; and automatically translating theATPG pattern data into ATE test pattern data.
 13. A method according toclaim 10 wherein the step of capturing includes the step: accumulatingmultiple sets of scan failure data.
 14. A method according to claim 10wherein the step of displaying includes: displaying textual/tabular scanfail data.
 15. A method according to claim 10 wherein the step ofdisplaying includes: displaying graphical scan fail data.
 16. A methodaccording to claim 10 and further including the step: displaying thediagnosis results data.
 17. A method according to claim 16 wherein thestep of displaying includes: displaying textual/tabular diagnosisresults data.
 18. A method according to claim 16 wherein the step ofdisplaying includes: displaying graphical diagnosis results data.
 19. Amethod according to claim 13 wherein the step of diagnosing includes thestep: automatically invocating the diagnosis tool on selected scanfailure data sets.
 20. A method according to claim 13 wherein the stepof diagnosing includes the step: generating ATPG pattern data in theATPG domain with the diagnosis tool; and automatically translating theATE output test data into ATPG data; and generating ATPG input diagnosistool data.
 21. A method according to claim 13 wherein the step ofdiagnosing includes the step: accumulating multiple sets of diagnosisresults data.
 22. A computer-readable medium having stored thereonsequences of instructions which, when executed, cause one or moreelectronic systems to: generate pattern signals in the ATE domain with asemiconductor tester to test a device-under-test and produce test outputdata in the ATE domain; generate ATPG pattern data and ATPG results datain the ATPG domain with an ATPG diagnosis tool; and automaticallycorrelate data between the ATPG domain and the ATE domain with atranslator to allow data communication between the tester and the tool.23. A method comprising: generating pattern signals in the ATE domainwith a semiconductor tester to test a device-under-test and produce testoutput data in the ATE domain; generating ATPG pattern data and ATPGresults data in the ATPG domain with an ATPG diagnosis tool; andautomatically correlating data between the ATPG domain and the ATEdomain with a translator to allow data communication between the testerand the tool.